1. Field of the Invention
The present invention relates to a method of manufacturing memory devices, and more particularly, to a method for fabricating memory devices using a dual damascene process and support devices using a single damascene process on a common semiconductor substrate.
2. Description of the Related Art
Flash memory devices, such as erasable and programmable read-only memory (EPROM) devices and electrically erasable and programmable read-only memory (EEPROM) devices, generally have a structure such that a control gate of a flash memory device is disposed on top of a floating gate of the flash memory device. In a conventional flash memory device, a floating gate is first formed and then a control gate is formed on top of the floating gate. Due to such a structure, a conventional flash memory device has a non-planar surface. In other words, the surface (particularly, the top surface of a control gate) of a flash memory device is higher than that of a support device. When patterning a control gate of a flash memory device, the surface of the flash memory device is not planar due to existence of a floating gate of the flash memory device. Such a non-planar surface of a flash memory device causes a patterning problem in lithography and/or an etching process for fabricating flash memory devices. For example, in lithography for a flash memory device, lithography resolution is deteriorated due to non-planar (i.e., high topography) surface of the flash memory device. Such a lithography resolution can be improved when the surface of the flash memory device has relatively less topography. Also, it is difficult in an etching process to optimize an etching selectivity between materials to be removed. and not to be removed due to a high topography of a memory device surface. The etching selectivity may be improved as the surface of a flash memory device is flatter, and be optimized in case of having a flat surface.
Thus, in a process of fabricating a conventional flash memory device, an extra process is required to planarize the non-planar surface of a flash memory device. The planarization of the surface of a flash memory device may advantageously induce a high quality metallic interconnection between a flash memory device and support devices, thereby achieving a high-density integration of the devices.
In a conventional flash memory device, properties of a gate dielectric layer of a flash memory device are different from those of support devices. A support device is a device disposed outside a memory array area. The support devices may include, for example, decoder circuits, sense amplifiers, drivers, and so on. Such differences in the properties between a flash memory device and support devices are inevitable because a flash memory device requires either hot-carrier injection or electron tunneling to program a floating gate of the flash memory device. In this case, the gate dielectric layer of a flash memory device has to be constantly programmed for an injection of electrons, whereas supporting devices do not require such a constraint.
In a conventional approach, this problem may be solved by fabricating each device independently on a common semiconductor substrate by separate processes. For example, a support device is formed by a first process, and then a flash memory device is formed by another process. This approach generally causes a significant increase in the process cost. Also, the conventional approach is highly complex for fabricating a flash memory integrated with support devices. Thus, it is difficult to improve yield for such a process.
Therefore, a need exists for a method of fabricating flash memory devices and support devices through an integrated process on a common semiconductor substrate, where the surfaces of the flash memory devices and the support devices are substantially coplanar. Further, it will be advantageous to enhance density and capability of integration of memory and support devices by employing the present invention for fabricating the devices together in an integrated process.
It is an object of the present invention to provide a method for fabricating memory devices on a common semiconductor substrate using a dual damascene process.
It is another object of the present invention to provide a method for fabricating memory devices and support devices together by an integrated process, wherein the memory devices and the support devices are formed by a dual damascene process and a single damascene process, respectively.
It is also another object of the present invention to provide a method for fabricating memory devices of which surfaces are substantially coplanar with those of support devices interconnected with the memory devices.
To achieve the above and other objects, the present invention provides a method for fabricating a flash memory by use of a dual damascene process, comprising the steps of forming at least one dummy gate structure for at least one memory device on the common semiconductor substrate, depositing dielectric material surrounding the at least one dummy gate structure on the common semiconductor substrate, etching the dielectric material and the at least one dummy gate structure to form at least one control gate void and at least one floating gate void for the at least one memory device, forming a gate dielectric layer on a bottom surface of the at least one floating gate void, depositing floating gate material on the gate dielectric layer in the at least one floating gate void to form a floating gate of the at least one memory device, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the at least one control gate void to form a control gate of the at least one memory device. The etching step preferably includes the steps of recessing the at least one dummy gate structure to form a recessed dummy floating gate with a predetermined height from the common semiconductor substrate, forming resist masks on the dielectric material deposited at the surroundings of the at least one dummy gate structure, selectively etching the dielectric material to form the at least one control gate void, and removing the recessed dummy floating gate to form the at least one floating gate void. The etching step may alternatively include the steps of removing the at least one dummy gate structure by an etching to form at least one void area, forming an oxide layer on a bottom surface of the at least one void area, depositing polysilicon material on the oxide layer to form a dummy floating gate with a predetermined height in the at least one void area, forming resist masks on the dielectric material deposited at the surroundings of the at least one dummy gate structure, selectively etching the dielectric material to form the at least one control gate void, and removing the dummy floating gate to form the at least one floating gate void. The etching step may also include the step of forming step edges between the at least one control gate void and the at least one floating gate void.
The method of the present invention may further include the steps of forming at least one gate conductor structure for at least one support device on the common semiconductor substrate, and depositing dielectric material at surroundings of the at least one gate conductor structure on the common semiconductor substrate. The step of forming the at least one gate conductor structure preferably includes the steps of forming a gate oxide layer of the at least one support device on the common semiconductor substrate, depositing control gate material on the gate oxide layer to form a control gate of the at least one support device, and forming a cap layer of the at least one support device on a top surface of the control gate material. The at least dummy gate structure for the at least one memory device and the at least one gate conductor structure for the at least one support device are formed an integrated process, including the steps of forming a gate oxide layer of the at least one dummy gate structure and the gate oxide layer of the at least one support device by a same process flow, depositing dummy material of the at least one dummy gate structure and the control gate material of the at least one support device by a same process flow, and forming a cap layer of the at least one dummy gate structure and the cap layer of the at least one support device by a same process flow.
The present invention also provides a method for fabricating memory devices on a common semiconductor substrate, comprising the steps of forming at least one dummy gate structure for at least one memory device on the semiconductor substrate, depositing dielectric material at surroundings of the at least one dummy gate structure on the common semiconductor substrate, removing the at least one dummy gate structure to form a void area on the common semiconductor substrate, forming a gate dielectric layer on a bottom surface of the void area, depositing floating gate material on the gate dielectric layer in the void area, forming resist masks on the dielectric material deposited at the surroundings of the at least one dummy gate structure, non-selectively etching the dielectric material and the floating gate material to form a floating gate and a control gate void, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the control gate void to form a control gate.
The present invention further provides a memory circuit having a plurality of memory cells formed on a common semiconductor substrate, wherein a memory cell comprising a channel region for the memory cell formed in the common semiconductor substrate, a gate oxide layer formed on the channel region, the gate oxide layer having a thickness unique to the memory cell, a floating gate formed on the gate oxide layer, where the floating gate having a predetermined thickness, a dielectric layer formed on the floating gate, and a control gate formed on the dielectric layer. The memory circuit preferably further includes at least one support device formed on the common semiconductor substrate by a process integrated with forming the memory device, wherein the at least support device includes a gate oxide layer having properties substantially equal to those of the gate oxide layer of the memory cell, a control gate formed on the gate oxide layer, the control gate having properties substantially equal to those of the floating gate of the memory cell, and a cap layer formed on the control gate. Preferably, top surfaces of the memory cells and the support devices are substantially coplanar.